After you install a Windows Vista Service Pack on a computer that is running Windows Vista, a hardware device does not work correctly. Additionally, if you open Device Manager, you might see an exclamation point next to the name of the hardware device.
The employee is highly skilled and is proficient in the theoretical and practical application of highly specialized information to computer systems analysis, programming, and software engineering. A job title shall not be determinative of the applicability of the exemption.
Computer Hardware And Software Exercises For Back
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Computer network architecture defines the physical and logical framework of a computer network. It outlines how computers are organized in the network and what tasks are assigned to those computers. Network architecture components include hardware, software, transmission media (wired or wireless), network topology, and communications protocols.
Processes for authenticating users with user IDs and passwords provide another layer of security. Security includes isolating network data so that proprietary or personal information is harder to access than less critical information. Other network security measures include ensuring hardware and software updates and patches are performed regularly, educating network users about their role in security processes, and staying aware of external threats executed by hackers and other malicious actors. Network threats constantly evolve, which makes network security a never-ending process.
Processor (CPU) is the active partof the computer, which does all the work of data manipulation anddecision making.Datapath is the hardware that performsall the required operations, for example, ALU, registers, and internalbuses.Control is the hardware that tells thedatapath what to do, in terms of switching, operation selection, datamovement between ALU components, etc.The processor represented by the shaded block inFigure 4.1 is organized as shown in Figure 4.2. Observe that the ALUperforms I/O on data stored in the register file, while the ControlUnit sends (receives) control signals (resp. data) in conjunction withthe register file.Figure 4.2. Schematic diagram of the processor in Figure 4.1,adapted from [Maf01].
Register Access takes input from the register file, to implement the instruction fetch or data fetch step of the fetch-decode-execute cycle. Calculate Branch Target - Concurrent with ALU #1's evaluation of the branch condition, ALU #2 calculates the branch target address, to be ready for the branch if it is taken. This completes the decode step of the fetch-decode-execute cycle. Evaluate Branch Condition and Jump to BTA or PC+4 uses ALU #1 in Figure 4.9, to determine whether or not the branch should be taken. Jump to BTA or PC+4 uses control logic hardware to transfer control to the instruction referenced by the branch target address. This effectively changes the PC to the branch target address, and completes the execute step of the fetch-decode-execute cycle.Figure 4.9. Schematic diagram of the Branch instructiondatapath. Note that, unlike the Load/Store datapath, theexecute step does not include writing of results back to theregister file [MK98].
Reading Assignments and Exercises While the finite state control for the multicycledatapath was relatively easy to design, the graphical approach shownin Section 4.4 is limited to small control systems. We implementedonly five MIPS instruction types, but the actual MIPS instruction sethas over 100 different instructions. Recall that the FSC of Section4.4 required 10 states for only five instruction types, and had CPIranging from three to five. Now, observe that MIPS has not only 100instructions, but CPI ranging from one to 20 cycles. A control system for a realistic instruction set (even if it is RISC)would have hundreds or thousands of states, which could not berepresented conveniently using the graphical technique of Section 4.4.However, it is possible to develop a convenienttechnique of control system design and programming by usingabstractions from programming language practice. This technique,called microprogramming, helps make control design moretractable and also helps improve correctness if good softwareengineering practice is followed. By using very low-levelinstructions (called microinstructions) that set the valueof datapath control signals, one can write microprogramsthat implement a processor's control system(s). To do this, onespecifies:Microinstruction Format that formalizes the structure and content of the microinstruction fields and functionality; Sequencing Mechanism, which determines whether the next instruction, or one indicated by a branch control structure, will be executed; and Exception Handling that determines what actions control should take when an error occurs (e.g., arithmetic overflow).We consider these issues, as follows.4.5.1. Microinstruction FormatA microinstruction is an abstraction of low-levelcontrol that is used to program control logic hardware. Themicroinstruction format should be simple, and should discourage orprohibit inconsistency. (An inconsistent microinstruction requires agiven control signal to be set to two different values simultaneously,which is physically impossible.)The implementation of each microinstruction should,therefore, make each field specify a set of nonoverlapping values.Signals that are never asserted concurrently can thus share the samefield. Table 4.5 illustrates how this is realized in MIPS, usingseven fields. The first six fields control the datapath, while thelast field controls the microinstruction sequencing (deciding whichmicroinstruction will be executed next).Table 4.5. MIPS microinstruction format [MK98].Field NameField FunctionALU controlSpecify the operation performed by the ALU during this clock cycle, the result written to ALUout.SRC1Source for the first ALU operandSRC2Source for the second ALU operandRegister controlSpecify read or write for Register File, as well as the source of a value to be written to the register file if write is enabled.MemorySpecify read or write, and the source for a write. For a read, specify the destination register.PCWrite controlSpecify how the PC is to be written (e.g., PC+4, BTA, or JTA)SequencingSpecify how to choose the next microinstruction for executionIn hardware, microinstructions are usually stored ina ROM or PLA (per descriptions in Appendices B and C of the textbook).The microinstructions are usually referenced by sequential addreses tosimplify sequencing. The sequencing process can have one of thefollowing three modes:Incrementation, by which the address of the current microinstruction is incremented to obtain the address of the next microinstruction. Thsi is indicated by the value Seq in the Sequencing field of Table 4.5. Branching, to the microinstruction that initiates execution of the next MIPS instruction. This is implemented by the value Fetch in the Sequencing field. Control-directed choice, where the next microinstruction is chosen based on control input. We call this operation a dispatch. This is implemented by one or more address tables (similar to a jump table) called displatch tables. The hardware implementation of dispatch tables is discussed in Section C.5 (Appendix C) of the textbook. In the current subset of MIPS whose multicycle datapath we have been implementing, we need two dispatch tables, one each for State 1 and State 2. The use of a dispatch table numbered i is indicated in the microinstruction by putting Dispatch i in the Sequencing field.Table 4.6 summarizes the allowable values for each fieldof the microinstruction and the effect of each value.Table 4.6. MIPS microinstruction field values and functionality [MK98].Field Name Values for Field Field Functionality----------------- ---------------- ------------------------------------------------------------Label Any string Labels control sequencing, per p. 403 of the textbookALU control Add ALU performs addition operation Subt ALU performs subtraction operation Func code Instruction's funct field determines ALU operationSRC1 PC The PC is the first ALU input A Buffer register A is the first ALU inputSRC2 B Buffer register B is the second ALU input 4 The constant 4 is the second ALU input (for PC+4) Extend Output of sign extension module is second ALU input Extshft Sign-extended output of two-bit shifter is second ALU inputRegister Control Read Read two registers using rs and rt fields of the current instruction, putting data into buffers A and B Write ALU Write to the register file using the rd field of the instruction register as the register number and the contents of ALUout as the data Write MDR Write to the register file using the rd field of the instruction register as the register number and the contents of the MDR as the dataMemory Read PC Read memory using the PC as the memory address, writing the result into the IR and MDR [implements instruction fetch] Read ALU Read memory using ALUout as the address, write the result into MDR Write ALU Write to memory using the ALUout contents as the address, writing to memory the data contained in buffer register BPCWrite control ALU Write the output of the ALU into the PC register ALUout-cond If the ALU's Zero output is high, write the contents of ALUout into the PC register Jump address Write the PC with the jump address from the instructionSequencing Seq Choose the next microinstruction sequentially Fetch Got to the first microinstruction to begin a new MIPS instruction Dispatch i Dispatch using the ROM specified by i (where i = 1 or 2)In practice, the microinstructions are input to amicroassembler, which checks for inconsistencies. Detectedinconsistencies are flagged and must be corrected prior to hardwareimplementation.4.5.2. Microprogramming the Datapath ControlIn this section, we use the fetch-decode-execute sequence that we developed for the multicycle datapath to designthe microprogrammed control. First, we observe that sometimesan instruction might have a blank field. This is permitted when:A field that controls a functional unit (e.g., ALU, register file, memory) or causes state information to be written (e.g., ALU dest field), when blank, implies that no control signals should be asserted. A field that only specifies control of an input multiplexer for a functional unit, when left blank, implies that the datapath does not care about what value the output of the mux has. We can now create the microprogram in stepwise fashion.4.5.2.1. Instruction Fetch and Decode, Data Fetch.Each instruction execution first fetches the instruction, decodes it, andcomputes both the sequential PC and branch target PC (if applicable). Thetwo microinstructions are given by: Label ALU control SRC1 SRC2 Register control Memory PCWrite Sequencing ----- ------------- ------ -------- ------------------- -------- --------- ------------ Fetch Add PC 4 --- Read PC ALU Seq --- Add PC Extshft Read --- --- Dispatch 1where "---" denotes a blank field. In the first microinstruction,ALU control, SRC1, and SRC2 are set to compute PC+4, which is written to ALUout. The memory field reads the instruction at address equal to PC, and stores the instruction in the IR. The PCWrite control causes the ALU output (PC + 4) to be written into the PC, while the Sequencing field tells control to go to the next microinstruction. The label field (value = fetch) will be used to transfer control in the next Sequencing field when execution of the next instruction begins. In the second microinstruction, we have the followingactions:ALU control, SRC1, and SRC2 are set to store the PC plus the sign-extended, shifted IR[15:0] into ALUout. Register control causes data referenced by the rs and rt fields to be placed in ALU input registers A and B. output (PC + 4) to be written into the PC, while the Sequencing field tells control to go to dispatch table 1 for the next microinstruction address. 4.5.2.2. Dispatch Tables. Patterson andHennessey consider the dispatch table as a case statementthat uses the opcode field and dispatch table i to selectone of Ni different labels. For in Dispatch Table#1 (i = 1, Ni = 4) we have label Mem1 for memory referenceinstructions, Rformat1 for arithmetic and logical instructions,Beq1 for conditional branches, and Jump1 for unconditionalbranches. Each of these labels points to a different microinstructionsequence that can be thought of as a kind of subprogram. Each microcodesequence can be thought of as comprising a small utility that implements the desiredcapability of specifying hardware control signals.4.5.2.3. Memory Reference Instructions. Threemicroinstructions suffice to implement memory access in terms of aMIPS load instruction: (1) memory address computation, (2) memoryread, and (3) register file write, as follows: Label ALU control SRC1 SRC2 Register control Memory PCWrite Sequencing ----- ------------- ------ -------- ------------------- -------- --------- ------------ Mem1 Add A Extend --- --- --- Dispatch 2 LW2 --- --- --- --- Read ALU --- Seq --- --- --- --- Write MDR --- --- FetchThe details of each microinstruction are given onpp. 405-406 of the textbook.4.5.2.4. R-format Execution. R-formatinstruction execution requires two microinstructions: (1) ALUoperation, labelled Rformat1 for dispatching; and (2) write toregister file, as follows: Label ALU control SRC1 SRC2 Register control Memory PCWrite Sequencing ----- ------------- ------ -------- ------------------- -------- --------- ------------ Rformat1 Func code A B --- --- --- Seq --- --- --- --- Write ALU --- --- FetchThe details of each microinstruction are given onp. 406 of the textbook.4.5.2.5. Branch and Jump Execution. Since weassume that the preceding microinstruction computed the BTA, themicroprogram for a conditional branch requires only the followingmicroinstruction: Label ALU control SRC1 SRC2 Register control Memory PCWrite Sequencing ----- ------------- ------ -------- ------------------- -------- --------- ------------ Beq1 Subt A B --- --- ALUout-cond Fetch Similarly, only one microinstruction is required to implement a Jumpinstruction: Label ALU control SRC1 SRC2 Register control Memory PCWrite Sequencing ----- ------------- ------ -------- ------------------- -------- --------- ------------ Jump1 --- --- --- --- --- Jump address Fetch Implementational details are given on p. 407 of thetextbook.The composite microprogram is therefore given by thefollowing ten instructions: Label ALU control SRC1 SRC2 Register control Memory PCWrite Sequencing ----- ------------- ------ -------- ------------------- -------- --------- ------------ Fetch Add PC 4 --- Read PC ALU Seq --- Add PC Extshft Read --- --- Dispatch 1 Mem1 Add A Extend --- --- --- Dispatch 2 LW2 --- --- --- --- Read ALU --- Seq --- --- --- --- Write MDR --- --- Fetch SW2 --- --- --- --- Write ALU --- Fetch Rformat1 Func code A B --- --- --- Seq --- --- --- --- Write ALU --- --- Fetch Beq1 Subt A B --- --- ALUout-cond Fetch Jump1 --- --- --- --- --- Jump address FetchHere, we have added the SW2 microinstruction toillustrate the final step of the store instruction.Observe that these ten instructions corresponddirectly to the ten states of the finite-state control developed inSection 4.4. In more complex machines, microprogram control cancomprise tens or hundreds of thousands of microinstructions, withspecial-purpose registers used to store intermediate data.4.5.3. Implementing a MicroprogramIt is useful to think of a microprogram as a textualrepresentation of a finite-state machine. Thus, a microprogram couldbe implemented similar to the FSC that we developed in Section 4.4,using a PLA to encode the sequencing function and main control.However, it is often useful to store the control function in a ROM,then implementing the sequencing function in some other way.Typically, the sequencer uses an incrementer to choose the nextcontrol instruction. Here, the microcode storage determines thevalues of datapath control lines and the technique of selecting thenext state. Address select logic contains dispatch tables (in ROMs orPLAs) and determines the next microinstruction to execute, albeitunder control of the address select outputs.This technique is preferred, since it substitutes asimple counter for more complex address control logic, which isespecially efficient if the microinstructions have little branching.Using a ROM, the microcode can be stored in its own memory and isaddressed by the microprogram counter, similar to regular programinstructions being addressed by an instruction sequencer. It is interesting to note that this is howmicroprogramming actually got started, by making the ROM and countervery fast. This represented a great advance over using slower mainmemory for microprogram storage. Today, however, advances in cachetechnology make a separate microprogram memory an obsoletedevelopment, as it is easier to store the microprogram in main memoryand page the parts of it that are needed into cache, where retrievalis fast and uses no extra hardware.4.5.4. Exception HandlingIf control design was not hard enough, we also haveto deal with the very difficult problem of implementing exceptionsand interrupts, which are defined as follows:An exception is an anomalous event arising from within the processor, such as arithmetic overflow. An interrupt is an event that causes an unexpected change in control flow. Interrupts are assumed to originate outside the processor, for example, an I/O request.In this discussion, we follow Patterson andHennessey's convention, for simplicity: An interrupt is an externallycaused event, and an exception one of all other events that causeunexpected control flow in a program. An interesting comparison ofthis terminology for different processors and manufacturers is givenon pp. 410-411 of the textbook.In this section, we discuss control design required tohandle two types of exceptions: (1) an indefined instruction, and (2)arithmetic overflow. These exceptions are germane to the small language (fiveinstructions) whose implementation we have been exploring thus far.4.5.4.1. Basic Exception Handling Mechanism.After an exception is detected, the processor's control circuitry mustbe able to (s) save the address in the exception counter (EPC) of theinstruction that caused the exception, then (2) transfer control to theoperating system (OS) at a prespecified address. The second step typically invokes an exception handler, which is a routine thateither (a) helps the program recover from the exception or (b) issues anerror message, then attempts to terminate the program in an orderlyfashion. If program execution is to continue after theexception is detected and handled, then the EPC register helpsdetermine where to restart the program. For example, theexception-causing instruction can be repeated byt in a way that doesnot cause an exception. Alternatively, the next instruction can beexecuted (in MIPS, this instruction's address is $epc +4).For the OS to handle the exception, one of twotechniques are employed. First, the machine can have Cause andEPC registers, which contain codes that respectively representthe cause of the exception and the address of the exception-causinginstruction. A second method uses vectored interrups , wherethe address to which control is transferred following the exception isdetermined by the cause of the exception. If vectored interrupts arenot employed, control is tranferred to one address only, regardless ofcause. Then, the cause is used to determine what action the exceptionhandling routine should take.4.5.4.2. Hardware Support. MIPS uses thelatter method, called non-vectored exceptions. To support thiscapability in the datapath that we have been developing in thissection, we need to add the following two registers:EPC: 32-bit register holds the address of the exception-causing instruction, and Cause: 32-bit register contains a binary code that describes the cause or type of exception.Two additional control signals are needed:EPCWrite and CauseWrite, which write theappropriate information to the EPC and Cause registers.Also required in this particular implementation is a 1-bit signal toset the LSB of Cause to be 0 for an undefined instruction, or 1for arithmetic overflow. Of further use is an address AEthat points to the exception handling routine to which control istransferred. In MIPS, we assume that AE =C000000016.In the previous datapath developed through Section4.4, the PC input is taken from a four-way mux that has three inputsdefined, which are: PC+4, BTA, and JTA. Without adding control lines,we can add a fourth possible input to the PC, namely AE,which is written to the PC by setting PCsource = 112.Unfortunately, we cannot simply write the PC into theEPC, since the PC is incremented at instruction fetch (Step 1 of themulticycle datapath) instead of instruction execution (Step 3) whenthe exception actually occurs. Thus, when an exception is detected,the ALU must subtract 4 from the PC and the ALUout register contentsmust be written to the EPC. It is fortunate that this requires noadditional control signals or lines in this particular datapathdesign, since 4 is already a selectable ALU input (used forincrementing the PC during instruction fetch, and is selected viaALUsrcB control signal).Hardware support for the datapath modificationsneeded to implement exception handling in the simple case illustratedin this section is shown in Figure 4.23. In the finite-state diagramsof Figure 4.24 and 4.25, we see that each of the preceding two typesof exceptions can be handled using one state each. For each exceptiontype, the state actions are: (1) set the Cause registercontents to reflect exception type, (2) compute and save PC-4 into theEPC to make avaialble the return address, and (3) write the addressAE to the PC so control can be transferred to the exceptionhandler. To update the finite-state control (FSC) diagram of Figure4.22, we ned to add the two states shown in Figure 4.24.Figure 4.23. Representation of the composite datapatharchitecture and control for the MIPS multicycle datapath, withprovision for exception handling [MK98]. 2ff7e9595c
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